Semiconductor device

ABSTRACT

A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge.

The present application is a Continuation of U.S. application Ser. No.13/116,670, filed on May 26, 2011, which is incorporated herein byreference in its entirety.

BACKGROUND

An integrated circuit (IC) typically is an electronic circuitmanufactured by diffusion of metal elements into the surface of asemiconductor material. Integrated circuits are used in variouselectronic devices today. Computers, cellular phones, and so forth aresome example devices which include integrated circuits and which havebeen made possible, at least in part, due to low cost of production ofsuch circuits.

For many applications, IC chips are packaged before being placed oncircuit boards. Materials used in chip manufacturing and packaging havedifferent properties and behaviors, and various temperature changes andmechanical stresses can lead to stress or damage in an end product. Forexample, stresses can cause damage to the IC chip. In particular,certain stresses can cause cracks in the IC chip, or more specifically,in a layer of passivation within the IC chip.

Various attempts have been made to identify specific causes of suchstresses and to address ways to avoid the stresses. For example, somepackage stress relief designs restrict the use of the areas which aremore heavily affected by stress. Some attempts to reduce stress haveproposed the use of various different materials or the use of definedpackaging methods, such as wire bonding and tape automated bonding,including single-point thermosonic bonding and gang or thermocompressionbonding. Different types of bonds or packaging can have a differenteffect on the stresses on the chip. However, some designs still exhibitareas of high stress with resultant cracking.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an example side view of a semiconductor device including abond pad;

FIG. 2a is a side view of a semiconductor device including a beveledtrace in accordance with an example of the present technology;

FIG. 2b is a side view of a semiconductor device including a beveledtrace and a plurality of layers intervening between the trace and asubstrate in accordance with an example of the present technology;

FIG. 3 is a top view of a semiconductor device in accordance with anexample of the present technology; and

FIG. 4 is a flow diagram of a method of forming a semiconductor devicein accordance with an example of the present technology.

DETAILED DESCRIPTION

Reference will now be made to the examples illustrated, and specificlanguage will be used herein to describe the same. It will neverthelessbe understood that no limitation of the scope of the technology isthereby intended. Additional features and advantages of the technologywill be apparent from the detailed description which follows, taken inconjunction with the accompanying drawings, which together illustrate,by way of example, features of the technology.

Integrated circuits (ICs) or dies can be fabricated using various layersand materials to make specific electrical circuit components and providefunctions for a semiconductor device. Layers for an IC can include metallayers for capacitors and connecting circuits, dielectric or insulationlayers for capacitors and transistors and electrical insulation betweenconducting layers, diffusion layers for forming transistors, protectionor passivation layers to protect the circuit from the environment,and/or a resistive layer for heat generation.

Semiconductor devices are often fabricated in large numbers and smallsizes. To facilitate electrical connections to the semiconductordevices, bond pads or bonding pads are fabricated for or with thesemiconductor device. A bond pad is a metallized area on the surface ofa semiconductor device to which connections can be made. FIG. 1illustrates an example semiconductor device 100 including a bond pad130. The device includes a substrate 110 upon which various layers 115,120, 125 are formed. For example, the layers can include a desirednumber of dielectric and metallic layers. At least one of the metalliclayers can be a metal wire or trace 120 which is connected to metallayers forming the bond pad. A passivation layer 125 can be formedbetween the trace and the bond pad. The bond pad and the trace can beinterconnected by etching one or more holes, called vias 127, in thepassivation layer. A metal, such as tungsten, can be deposited in thevia, or alternatively, at least one of the metal layers forming the bondpad can be allowed to fill the via as the metal layer is deposited.

As shown in FIG. 1, the metal trace 120 extends under the bond pad 130above. Due to packaging and other stresses, as well as softness of themetal used in the bond pad above the trace, one or more metal layersand/or dielectric layers in the bond pad can crack and fail. Also, FIG.1 illustrates a square-ended metal trace 122. The squared trace end canlead to stress concentration on the passivation layer 125, which cancause dielectric or metal cracking and failure.

FIG. 2a illustrates an example semiconductor device 200 having featureswhich result in a more reliable device due to decreased stresses andchances of cracking and failure. The device of FIG. 2a includes asubstrate 210. The substrate can include silicon, gallium arsenide, orother elements and compounds used in semiconductor wafers and dies. Aplurality of layers 220, 225, 230 can be formed on the substrate. Forexample, the layers can be formed using various deposition, etching,and/or lithography techniques. As specific and non-limiting examples offabrication methods, various metal, dielectric, and other layers may bedeposited using sputtering or evaporation processes, physical vapordeposition, chemical vapor deposition, electrochemical deposition,molecular beam epitaxy, and/or atomic layer deposition. Photolithographyand masks may be used to pattern dopants and other layers.Photolithography may be used to protect or expose a pattern to etchingwhich can remove material from the conductive or metal layer, theresistive layer, the dielectric layer, the passivation layer, thepolymer layer, and other layers. Etching may include wet etching, dryetching, chemical-mechanical planarization (CMP), reactive-ion etching(RIE), deep reactive-ion etching (DRIE), etc. Etching may be isotropicor anisotropic. The resulting features from deposition and etching oflayers can be resistors, capacitors, sensors, contact pads, wires,traces, and so forth that can connect devices and resistors together.

A trace layer 220 can be formed or positioned in proximity to thesubstrate 210. The trace layer can include a metallic trace forsupplying an electrical connection to the semiconductor device 200. Forsimplicity, FIG. 2a illustrates the trace layer being formed directly onthe substrate. However, in practice, and as shown in FIG. 2b , thedevice can include any suitable number of intervening layers 215.

FIG. 2b illustrates an example configuration where the device 201includes a plurality of dielectric layers 216, 218 and an additionalmetallic layer 217 intervening between the trace layer and thesubstrate. The dielectric layers can include any of a variety ofdifferent dielectric materials individually or in combination. Someexample dielectric layers include silicon, such as in silicon dioxide,tetraethyl orthosilicate, silicate glass (including undoped silicateglass, phospho-silicate glass, boro-silicate glass, andboro-phospho-silicate glass), silicon oxycarbide, silicon carbide,silicon nitride, and so forth. Some other examples include aluminumoxide and hafnium oxide. The dielectric layers may be selected accordingto a desired dielectric constant, typically between about 2.0 and 4.0.

The metallic trace 225 can include a suitable material, such as aluminumor copper. In one example, the trace layer can be deposited as a blanketfilm of aluminum. The aluminum film can be patterned and etched to formone or more isolated wires as the trace. For simplicity, the wireremaining as the trace can be considered the trace can be considered tobe the trace layer unless otherwise indicated. For some applications,aluminum may result in timing delays and the trace can be formed ofcopper. Devices including copper traces can be formed using damasceneprocessing, such as single or double damascene processing. In someexamples damascene processing can eliminate one or more processing stepsand provide certain efficiencies over processing of aluminum wires.

At least a portion of the trace 225 can be beveled. In other words, thetrace can include a beveled edge 222. Integration of bond pad designswith micro-electro-mechanical systems (MEMS) structures often involvescovering a thick metal trace layer with a thin dielectric or passivationlayer. In fabrication of at least some of these devices, a photosequence is used to create certain device features. For example, whenthe semiconductor device includes a thermal inkjet resistor, a photosequence can be performed during fabrication to create resistor bevels.This existing photo sequence can be simultaneously used to bevel aleading edge of the metal trace to prevent or limit cracking in thepassivation layer. Such a sequence or process can be used to bevel thetrace whether or not a device fabrication process already includes thesequence or process. In one example, a dry resistor etch (DRE) mask canbe applied to bevel the trace(s). In the example including the thermalinkjet resistors, a DRE mask can be used to bevel traces and createthermal inkjet resistor bevels substantially simultaneously. Where aprocess exists in device fabrication for beveling another part of thedevice, beveling of the trace can be accomplished without significantexpenditures of time or money in retooling, reprogramming, or otherwisechanging the fabrication process. Essentially, the change can beimplemented with a one-time cost and effort in creating a photo maskwhich includes the beveling of the trace.

A mask can be applied after deposition of the trace to create bevelededges about a perimeter of openings in the trace film. In one example,the mask can create a beveled edge at one end of the trace. In anotherexample, application of the mask can result in beveling of a pluralityof edges of the trace. The bevel can be created in a variety ofconfigurations. For example, the bevel can be a curved bevel or astraight bevel. The bevel can be angled anywhere between 5° and 90° withrespect to a plane of the substrate or with respect to a plane of anintervening layer between the trace and the substrate. For example, thebevel may be angled at 15°, 30°, 45°, 60°, or 75°. FIGS. 2a-2billustrate a trace 220 with a beveled edge 222 beveled at approximately45° with respect to a plane of the substrate 210.

With the mask in place, a bevel can be etched into the trace using asuitable metal etchant that acts upon exposed portions of the tracematerial and not upon the mask. As described above, the etchant can workupon the plane of the trace to etch the trace at an angle. The etchingprocess can continue with the trace etched downwardly at an angle untila desired depth is reached. The photomask can maintain the boundaries ofthe trace as well as protect the underlying layers and/or componentsfrom potentially deleterious effects of the etchant.

A non-conductive thin film layer, or passivation layer 225, can beformed over the trace layer 220. The passivation layer can include adielectric material. In more specific examples, the passivation layercan include a deposit of silicon nitride and/or silicon carbide. A via227 can be etched through the passivation layer to the trace. A metal,such as tungsten, can then be deposited in the via, such as by using asputtering or evaporation process. Alternatively, the via can be filledby the metal of one of the metal layers of the bond pad when the metalis deposited to form a layer of the bond pad. A plurality of conductivelayers 232, 234 can be positioned in proximity the trace layer to formthe bond pad 230. For example, the passivation layer can be interposedbetween the trace layer and the plurality of conductive layers. Anelectrical connection is enabled between the trace and the bond pad bythe via through the passivation layer.

In more detailed examples, the bond pad can have width and lengthdimensions of approximately 100×200 μm. The plurality of conductivelayers forming the bond pad can include two layers. A first or lowerlayer, being closer to the passivation layer, may comprise tantalum. Asecond or upper layer may comprise gold. The first layer can preventdegradation of the passivation layer that might occur if the passivationlayer were directly exposed to the metal etching or other fabricationprocesses that defines the second layer contact pad. The first andsecond layers can be rectangularly shaped. The first layer can have alarger circumference than the second layer. For example, the first layercan have a width and/or length at least approximately 6 μm greater thanthe width and/or length of the second layer. The second layer can becentered over the first layer, at least in one direction, such that thelower layer extends at least approximately 3 μm past the edges of thesecond layer on either side of the second layer in the at least onedirection when viewed from above.

Referring to FIG. 3, a top view of a semiconductor device 300 isillustrated which includes a substrate having a plurality of layersthereon including a trace layer 310, and a bond pad (including layers315, 320) formed above the plurality of layers. The bond pad includestwo rectangularly shaped layers, a lower layer 315 of which has a largercircumference than an upper layer 320 thereof. Some devices can includea via which extends beneath a majority of a length of a bond pad (see127 of FIG. 1, for example). However, as illustrated in FIGS. 2a-2b andFIG. 3, the present device can include a via 325 which has a lengthgreater than a width. In other words, the via can be positioned inproximity to a side of the bond pad and comprise a via length L_(V) (inthe length direction of the bond pad L_(B)) extending along the side ofthe bond pad which is greater than a width W_(V) of the via (in thewidth direction of the bond pad W_(B)). Also, FIG. 3 illustrates a point330 at which the trace terminates with respect to the bond pad. Invarious implementations, the trace can be formed at least as wide as thevia, or wider or more narrow than the bond pad. FIG. 3 illustrates anexample where the trace is wider than the via and also wider than thebond pad. The trace can extend beneath the bond pad along a fraction ofa length of the bond pad. For example, the trace can extend along lessthan ½ of the bond pad length L_(B), or less than ⅓, ¼, ⅕, or 1/10 ofthe bond pad length L_(B). To the extent the trace extends beneath thebond pad, the via can be appropriately sized, shaped, and/or positionedto enable electrical connection between the trace and the bond pad. Inone aspect, the via can be etched with a rectangle, oval, circle, orpolygonal shape with squared and/or rounded corners.

Referring to FIG. 4, a flow diagram of a method 400 of forming asemiconductor device is shown in accordance with an example. The methodcan include forming 410 a trace layer above a surface of a substrate,the trace layer comprising a trace for supplying an electricalconnection to a bond pad of the semiconductor device. A mask can beapplied 420 to the trace layer to bevel an edge of the trace. In oneaspect, a plurality of edges of the trace can be beveled using the mask.

A non-conductive thin film layer can be deposited 430 above the tracelayer. The thin film layer can include a via to enable the electricalconnection from the trace to the bond pad. The method can furtherinclude depositing 440 a plurality of conductive layers above the thinfilm layer to form the bond pad such that an electrical signal from thetrace is receivable by at least one of the plurality of conductivelayers through the via. In one aspect, the conductive layers forming thebond pad can be formed by depositing a tantalum layer and subsequentlydepositing a gold layer. The gold layer can be deposited with a smallersurface area than a surface area of the tantalum layer.

The method can include forming the via in the thin film layer by etchingan elongate area proximate to a side of at least one of the plurality ofconductive layers. The method can include forming the trace layer bydepositing aluminum as the trace from a location not between thesubstrate and the bond pad (or where the bond pad will be subsequentlyformed) to a location between the substrate and an edge of the bond padas illustrated in FIGS. 2a -3. The location between the substrate andthe edge of the bond pad can be at a point less than half of a length ofthe bond pad or less than a fourth of a length of the bond pad, etc.

In some examples, the semiconductor device can include transistor and/orresistor components formed in or with the substrate or layers above thesubstrate. For example, the substrate can include a transistor gate,source, and drain. A first dielectric layer can be deposited over andisolate the transistor gate, source, drain and substrate. The firstdielectric layer can be patterned and etched to provide one or moreopenings to enable a subsequently deposited metal layer to contact thetransistor source, drain, and gate, as well as the substrate.

A first metal layer including one or more metals can be deposited overthe first dielectric layer. The first metal layer can be patterned usinga photomask and subsequently etched for the purpose of providingresistive and conductive material for other layers such as heattransducer and/or conductive layers. In a specific example, the firstmetal layer can include metals deposited in sequence using a same metaldeposition tool, with a resistive material comprising tantalum aluminideand a conductive material comprising an aluminum copper alloy. A maskcan be applied to the first metal layer to pattern the first metal layerto form a trace.

A second dielectric layer can be deposited over the first metal layer.The second dielectric layer can be patterned and etched to provide oneor more openings to enable a subsequently deposited metal layer tocontact the first metal layer. A second metal layer can be depositedover the second dielectric layer. The second metal layer, or tracelayer, can include, for example, a layer of aluminum. A mask and metaletchant can be applied to form the trace wire(s), as well as to bevel anedge of the trace.

A layer of passivation material can be deposited, which can cover andprotect the trace. The passivation layer can be applied over the secondmetal layer and the second dielectric layer and extends near the seconddielectric layer edges.

After the passivation layer is applied, a long, narrow via can be formedthrough the passivation layer. Metal layers such as those describedabove can be deposited and etched over the passivation layer.

There may be many other possible variations available for fabricatingthe device and device components. Such variations and adaptations arealso contemplated and considered within the scope of this disclosure.

Although the foregoing description has focused primarily on theproduction and product of semiconductor devices using aluminum tracesand also of semiconductor devices for use in thermal inkjet printing, itwill be appreciated that the present invention may also be applied tothe production of semiconductor devices using different materials andused for any of a variety of applications, including but not limited toaerosols suitable for pulmonary delivery of medicine, scent delivery,dispensing precisely controlled amounts of pesticides, paints, fuels,etc.

By arranging a trace to extend under one end of a bond pad as opposed toextending under substantially an entire length of the bond pad, crackingin the bond pad can be prevented or reduced. Also, where an end of atrace underlying a bond pad is squared, pressure from the bond can beconcentrated and result in passivation cracking. However, by beveling anend of the trace (before depositing a passivation layer), pressure fromthe bond can be reduced. Thus, likelihood of passivation cracking issimilarly reduced.

While the forgoing examples are illustrative of the principles of thepresent technology in one or more particular applications, it will beapparent to those of ordinary skill in the art that numerousmodifications in form, usage and details of implementation can be madewithout the exercise of inventive faculty, and without departing fromthe principles and concepts of the technology. Accordingly, it is notintended that the technology be limited, except as by the claims setforth below.

The invention claimed is:
 1. A semiconductor device, comprising: asubstrate; a trace layer positioned in proximity to the substrate andincluding a trace for supplying an electrical connection to thesemiconductor device; a plurality of intervening layers between thesubstrate and the trace layer; a plurality of conductive layerspositioned in proximity the trace layer and forming a bond pad; a viabetween the trace layer and at least one of the plurality of conductivelayers to enable the electrical connection from the trace to the bondpad; and wherein a portion of the trace between the substrate and theplurality of conductive layers comprises a beveled edge.
 2. A device asin claim 1, wherein the plurality of conductive layers comprises a layerof gold and a layer of tantalum.
 3. A device as in claim 2, wherein thetantalum layer is positioned between the substrate and the gold layer.4. A device as in claim 2, wherein the tantalum layer comprises a largersurface area than the gold layer.
 5. A device as in claim 1, wherein thetrace layer comprises aluminum.
 6. A device as in claim 1, wherein thevia is positioned in proximity to a side of the bond pad and comprises alength extending along the side of the bond pad greater than a width ofthe via.
 7. A device as in claim 1, wherein the trace layer extendsbetween the substrate and the plurality of conductive layers and extendsalong less than half of a length of at least one of the plurality ofconductive layers.
 8. A device as in claim 1, wherein the beveled edgecomprises a 45° bevel.
 9. A device as in claim 1, wherein the pluralityof intervening layers comprise a dielectric layer.
 10. A device as inclaim 9, wherein the dielectric layer comprises silicon, silicondioxide, tetraethyl orthosilicate, silicate glass, undoped silicateglass, phospho-silicate glass, boro-silicate glass,boro-phospho-silicate glass, silicon oxycarbide, silicon carbide,silicon nitride, aluminum oxide, or hafnium oxide.
 11. A device as inclaim 9, wherein the dielectric layer has a dielectric constant fromabout 2.0 and 4.0.
 12. A device as in claim 1, wherein the plurality ofintervening layers include a metallic layer.
 13. A device as in claim 1,wherein the plurality of intervening layers include a dielectric layerand a metallic layer.
 14. A device as in claim 1, wherein the pluralityof intervening layers comprise two dielectric layers having a metalliclayer positioned therebetween.